Xilinx jtag configuration driver#
The Linux device driver is located in the src/driver directory of the repository. The following block diagrams illustrate prototype systems which includes the Xilinx Debug Bridge IP core together with a minimal binary counter connected to a System ILA to verify operation of the system. A Xilinx board was used for the prototype tests the wiki is based on. HardwareĪ embedded system is built in Vivado which requires a CPU capable of running Linux (Cortex A9, Cortex A53, MicroBlaze) together with the peripherals for a networked device (Ethernet). The solution should be portable such that it will run on any Xilinx CPU, but testing has only been done on the ARM CPUs which run Linux. The solution is made up of a hardware design running on a board with a Xilinx SoC or FPGA together with a Linux device driver and a Linux application running on a CPU of the SoC or FPGA. The 2020.1 version of Xilinx tools including Vivado and PetaLinux were used for the prototype build of the hardware and software. The concept is similar to what is described in this wiki page, but rather than Ethernet, PCIe is used. XVC over PCIe is more common in a data center application where there is a PCIe accelerator card. This wiki page will not describe XVC over PCIe. Users are expected to have background knowledge of Linux, embedded systems, and networking. This wiki page is intended to illustrate details of the Xilinx Virtual Cable but is not intended to be a tutorial for any of the tools that are used such as Vivado and PetaLinux. This primary difference was enabled with the introduction of the Debug Bridge IP within the IP Catalog. In this wiki article, the Target FPGA is the Programmable Logic within the Zynq/ZynqMP SoC device. In XAPP1251 the target FPGA was another device and it was being accessed via JTAG pins from GPIO of the master FPGA. One of the major differences in the implementation between XAPP1251 and this article, is location of the target FPGA.
Xilinx jtag configuration update#
This wiki page is designed to be an update to the application note without duplicating information that has not changed. Since that time, the solution has evolved to be cleaner and simpler using IP available in Vivado and source code from a GitHub repository. The Xilinx Virtual Cable started as an application note, XAPP1251, a number of years ago. This can be advantageous for in-field debugging or during stress test scenarios where JTAG is not an option. This enables a user to access a Xilinx device through another medium (In this case we use Ethernet) instead of needing a dedicated JTAG cable. The Xilinx Virtual Cable (XVC) is a TCP/IP-based protocol that acts like a JTAG cable and provides a means to access and debug your FPGA or SoC design without using a physical cable.